In integrated circuits (ICs), such as CMOS (i.e., complementary metal-oxide-semiconductor) RFIC (i.e., radio frequency integrated circuit), inductors are important circuitry component. Performance parameters of the inductors may directly affect the performance of the ICs. Current ICs often include planar inductors such as, for example, planar spiral inductors. A planar inductor can be formed by winding conductive metal wires on surface of a substrate or a dielectric layer of an IC device. Compared with other conventional wire-winding inductors, a planar inductor typically has low cost with ease of device integration, low noise, and low power consumption. More importantly, planar inductors are compatible with current ICs.
Quality factor (Q) of an inductor device can be defined as a ratio of the energy stored in the inductor to the energy loss per oscillation cycle. Therefore, the higher the quality factor (Q) of the inductor device, the higher the efficiency and the performance can be. Conventional planar inductors, however, have low Q, which leads to poor inductor performance and thereby affects performance of the IC devices. Additionally, in standard CMOS processing, the metal wirings of a spiral inductor can have high resistance. This may cause a large silicon substrate loss at high frequencies. Thus, the quality factor (Q) of a silicon-based spiral inductor is generally low.
Electric field generated in the inductor may induce opposite charges at corresponding parts of the substrate, and AC voltage difference between different parts of the inductor may induce AC voltage difference between the corresponding parts of the substrate. For a semiconductor substrate, such voltage difference can generate a current called capacitive coupling substrate current, which may cause ohmic losses.
Even though a planar spiral and a vertical stacked inductor are both compatible with IC interconnect structures, magnetic field generated from such inductors can pass vertically through the substrate. According to Lenz's law, an alternating magnetic field of the inductor can induce an alternating eddy current on the substrate. The eddy current can dissipate the electric energy, which is converted from magnetic energy, through Joule heating. The eddy current flows in an opposite direction of the inductor current, thus the magnetic field induced by the eddy current is opposite to the magnetic field from the inductor. This may lower the inductance of the inductor.
Standard CMOS substrate is a semiconductor. At high frequencies, the substrate loss is the major contributor to the inductor loss. Currently, a ground shield is commonly used to reduce the substrate loss of an inductor.
FIG. 1 shows a top view of a conventional ground shield. As shown in FIG. 1, the ground shield includes a ground ring 10 and a pattern 20 disposed within the ground ring. The pattern 20 can be made of a semiconductor material. Since the pattern 20 has a lower resistance than the substrate, it may terminate the electric field from the inductor and shield the electric field from going to the substrate. This may avoid generating a substrate current and lower the energy loss of the substrate. However, the pattern may induce a large coupling capacitance at high frequencies. In addition, the shield (e.g. pattern 20) has a large contact area in the middle, which may induce a large eddy current loss and reduce the quality factor (Q) of the inductor.